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CXG1053FN
Power Amplifier/Antenna Switch + Low Noise Amplifier/Down Conversion Mixer for PHS
Description The CXG1053FN is an MMIC consisting of the power amplifier, antenna switch, low noise amplifier and down conversion mixer. This IC is designed using the Sony's GaAs J-FET process featuring a single positive power supply operation. Features * Operates at a single positive power supply: VDD = 3V * Small mold package: 26-pin HSOF * Low current consumption: IDD = 150mA (POUT = 20.2dBm, f = 1.9GHz) * High power gain: Gp = 39dB Typ. (POUT = 20.2dBm, f = 1.9GHz) * Low current consumption: IDD = 2.5mA Typ. (When no signal) * Low noise: NF = 2.7dB Typ. (f = 1.9GHz) * High conversion gain: Gc = 9dB Typ. (f = 1.9GHz) * Low distortion: Input IP3 = +1dBm Typ. (f = 1.9GHz) Applications Japan digital cordless telephones (PHS) Structure GaAs J-FET MMIC 26 pin HSOF (Plastic)
Absolute Maximum Ratings * Supply voltage VDD * Voltage between gate and source VGSO * Drain current IDD * Allowable power dissipation PD Control voltage * Supply voltage * Input power
6 1.5 550 3
V V mA W
VCTL
6
V
VDD PRF
6 +10
V dBm
* Channel temperature Tch * Operating temperature Topr * Storage temperature Tstg
150 -35 to +85 -65 to +150
C C C
Note on Handling GaAs MMICs are ESD sensitive devices. Special handling precautions are required.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E99852-PS
CXG1053FN
Block Diagram and External Circuit
2.2nH PIN 14 13 (VGG1) 1k
15
12 100pF
VPCTL
VDD1 1nF VDD2 1nF VDD3 10nF
18nH
16 1nF
11 2.2nH
VGG2
18nH
17 30pF 18
10 1pF 9 30pF
(POUT)
1.8nH
(TX)
19
8 100pF
VCTL1
(RX) 30pF VCTL2 100pF (RFIN) 2.7nH 3.9nH
20
7 30pF
ANT
21
6 100pF 3.9nH 1.5nH 100pF 1nF
RFOUT VDD (RF AMP)
22
5
23 1nF 24
4 RFIN (MIX) VDD (LO AMP) LOIN
3
25 VDD (IF AMP) 56nH 1nF 8pF 100nF 26
2 18pF 1 1nF
IFOUT
Pin Configuration
PIN 14 GND 15 VDD1 16 VDD2 17 VDD3 18 GND 19 RX 20 VCTL2 21 RFIN 22 CAP 23 GND 24 CAP 25 IFOUT/VDD (IF AMP) 26 13 VGG1 12 VPCTL 11 VGG2 10 POUT 9 8 7 6 5 4 3 2 1 TX VCTL1 ANT GND RFOUT/VDD (RF AMP) GND RFIN (MIX) VDD (LO AMP) LOIN
-2-
CXG1053FN
Electrical Characteristics 1. Control Pin Logic for Antenna Switch Conditions of control pin VCTL1 = 3V, VCTL2 = 0V VCTL1 = 0V, VCTL2 = 3V ANT - TX ON OFF ANT - RX OFF ON
2. Power Amplifier Block + Antenna Switch Transmitter Block These specifications are when the Sony's recommended evaluation board with the external circuit shown on page 7 is used. Therefore, the power amplifier output pin (POUT) and the antenna switch transmission input pin (Tx) are connected via an external circuit. The specifications of the power amplifier block are set including the antenna switch transmitter block. Unless otherwise specified: VDD = 3V, VPCTL = 2V, VCTL1 = 3V, VCTL2 = 0V, IDD = 150mA, POUT = 20.2dBm, f = 1.9GHz, Ta = 25C Item Current consumption Gate voltage adjustment value Output power Power gain Adjacent channel leak power ratio (600 100KHz) Adjacent channel leak power ratio (900 100KHz) Occupied bandwidth 2nd-order harmonic level 3rd-order harmonic level IDD VGG POUT GP ACPR600kHz ACPR900kHz OBW -- -- Measured with the ANT pin Measured with the ANT pin Measured with the ANT pin Measured with the ANT pin Measured with the ANT pin Measured with the ANT pin 0 20.2 36 39 -63 -70 250 Symbol Measurement conditions Min. Typ. 150 0.25 0.6 Max. Unit mA V dBm dB -55 dBc -60 dBc 275 KHz -25 dBc -25 dBc
-3-
CXG1053FN
3. Antenna Switch Receiver Block + Front-end Block These specifications are when the Sony's recommended evaluation board with the external circuit shown on page 7 is used. Therefore, the antenna switch reception pin (Rx) and the low noise amplifier input pin (RFIN_LNA) are connected via an external circuit. The specifications of the low noise amplifier block are set including the antenna switch reception block. (a) Antenna switch receiver block + low noise amplifier block Unless otherwise specified: VDD = 3V, VCTL1 = 0V, VCTL2 = 3V, RF = 1.9GHz/-30dBm, Ta = 25C Item Current consumption Power gain Noise figure Input IP3 Isolation Symbol IDD_LNA GP NF IIP3 ISO 1 -11 25 Measurement conditions When no signal 12.5 Min. Typ. 2.5 14.5 2.7 -8 30 Max. 3.5 16.5 3.5 Unit mA dB dB dBm dB
1 Conversion from IM3 compression ratio during FR1 = 1.9000GHz/-30dBm and FR2 = 1.9006GHz/-30dBm input. (b) Mixer Block Unless otherwise specified: VDD = 3V, RF = 1.90GHz/-25dBm, LO = 1.66GHz/-12dBm, Ta = 25C Item LO block current consumption IF block current consumption Conversion gain Noise figure Input IP3 LO to ANT leak Symbol IDD_LO IDD_IF GC NF IIP3 PLK 2 3 -2 Measurement conditions When no signal When no signal 7 Min. Typ. 1.7 3.3 9 8.5 +1 -43 -38 Max. 2.5 4.5 11 11.5 Unit mA mA dB dB dBm dBm
2 Conversion from IM3 compression ratio during FR1 = 1.9000GHz/-25dBm and FR2 = 1.9006GHz/-25dBm input. 3 The RFOUT pin of the LNA and the RFIN pin of the MIX block is connected directly with the cable. And the power supply of the LNA is turned on. (c) Total of (a) + (b) Item Current consumption Symbol IDD_total Measurement conditions When no signal Min. Typ. 7.5 Max. 10 Unit mA
-4-
CXG1053FN
Example of Representative Characteristics 1. Power Amplifier + Antenna Switch Transmitter Block (f = 1.9GHz, Ta = 25C)
ACPR600kHz - Adjacent channel leak power ratio [dBc]
25
20 POUT - Output power [dBm]
15
Gp - Power gain [dB]
VDD = 3V, VPCTL = 2V, VGG = const., VTCL1 = 3V, VCTL2 = 0V IDD = 150mA (@POUT = 20.2dBm), PIN = var. POUT
-40
45 Gp
-40
-45
40
-45
-50
35 VDD = 3V, VPCTL = var., VGG = const., VTCL1 = 3V, VCTL2 = 0V IDD = 150mA (@VPCTL = 2V), PIN = var., POUT = 20.2dBm ACPR600kHz 20
-50
10
-55
30
-55
5 ACPR600kHz 0
-60
25
-60
-65
-65
-5 -40
-35
-30
-25
-20
-15
-70 -10
15 0.0
0.5
1.0
1.5
2.0
2.5
-70 3.0
PIN - Input power [dBm]
VPCTL - Gain control voltage [V]
ACPR600kHz - Adjacent channel leak power ratio [dBc]
23
22 POUT - Output power [dBm]
21
Gp - Power gain [dB]
VDD = var., VPCTL = 2V, VGG = const., VTCL1 = 3V, VCTL2 = 0V IDD = 150mA (@VDD = 3V, POUT = 20.2dBm), PIN = -19.2dBm POUT
-40
42
-45
41
VDD = 3V, VPCTL = 2V, VGG = var., VTCL1 = 3V, VCTL2 = 0V IDD = var., PIN = var., POUT = 20.2dBm Gp
-40
-45
-50
40
-50
20
-55
39
-55
19
ACPR600kHz
-60
38
ACPR600kHz
-60
18
-65
37
-65
17 2.0
2.5
3.0
3.5
4.0
4.5
-70 5.0
36 100
120
140
160
180
200
-70 220
VDD - Supply voltage [V]
IDD - Current consumption [mA]
-5-
ACPR600kHz - Adjacent channel leak power ratio [dBc]
POUT, ACPR600kHz vs. VDD
Gp, ACPR600kHz vs. IDD
ACPR600kHz - Adjacent channel leak power ratio [dBc]
POUT, ACPR600kHz vs. PIN
Gp, ACPR600kHz vs. VPCTL
CXG1053FN
2. Antenna Switch Receiver Block + Low Noise Amplifier, Down Conversion Mixer (Ta = 25C)
SW/LNA block: POUT, PIM3 vs. PIN
20 POUT - RF output power, PIM3 - 3rd-order intermodulation power [dBm] VDD = 3V, RF1 = 1.9000GHz, RF2 = 1.9006GHz VCTL1 = 0V, VCTL2 = 3V POUT 20 POUT - IF output power, PIM3 - 3rd-order intermodulation power [dBm]
MIX block: POUT, PIM3 vs. PIN
VDD = 3V, RF1 = 1.9000GHz, RF2 = 1.9006GHz LO = 1.66GHz/-12dBm POUT -20
0
0
-20
-40
-40
-60 PIM3 -80 Input IP3 -100 -50 -40 -30 -20 -10 0
-60
PIM3
-80 Input IP3 -100 -40 -30 -20 -10 0 10
PIN - RF input power [dBm]
PIN - RF input power [dBm]
MIX block: Gc, NF vs. PLO
10.0 12 2.0
MIX block: Input IP3, PLK vs. PLO
-25 PLK - LO to ANT leak level [dBm]
9.5 Gc - Conversion gain [dB] Gc 9.0
11 NF - Noise figure [dB]
1.5 Input IP3 Input IP3 [dBm]
-30
10
1.0
-35
8.5 NF 8.0
9
0.5 PLK 0.0 VDD = 3V, RF = 1.90GHz/-25dBm, LO = 1.66GHz VCTL1 = 0V, VCTL2 = 3V LNA output pin and MIX input pin is directly connected with the cable. -20 -15 -10 -5 0
-40
8
-45
7.5 VDD = 3V, RF = 1.90GHz/small signal, LO = 1.66GHz 7.0 -25
7
-0.5
-50
6 -20 -15 -10 -5 0 PLO - LO input power [dBm]
-1.0 -25
-55
PLO - LO input power [dBm]
-6-
CXG1053FN
Recommended Evaluation Board
PAIN VPCTL
VGG
ANT
VDD-PA VCTL2
VCTL1 RFOUT_LNA VDD_LNA
IFOUT VDD_IF
VDD_LO
RFIN_MIX
LOIN
Glass fabric-base epoxy board (4 layers) Thinkness between layers 1 and 2: 0.2mm Dimensions: 50mm x 50mm
Enlarged Diagram of External Circuit Block
R1
C6 C6 L6 L6 C6 C7 L2 C4 L3
C5
R1 = 1k L1 = 1.5nH L2 = 1.8nH L3 = 2.2nH L4 = 2.7nH L5 = 3.9nH L6 = 18nH L7 = 56nH C1 = 1pF C2 = 8pF C3 = 18pF C4 = 30pF C5 = 100pF C6 = 1nF C7 = 10nF C8 = 100nF
C1 C4 C5 C4 L5 C5 L4 C6 C8 C2 C6 L7 C3 C5 C6 C5 L5 L1 L3 C4
C6
-7-
CXG1053FN
Package Outline
Unit: mm
HSOF 26PIN(PLASTIC)
0.9 0.1 0.08 *5.6 0.05 A 26 14 S 5.5 4.2
3.8 0.05
4.4 0.1
(1.5) (0.7)
0.5
1 0.4 0.07 M S A
13 S 0.2 4.4 0.2
Solder Plating 0.2 0.05
B + 0.05 0.14 - 0.03 DETAILB NOTE: Dimension "" does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE HSOF-26P-01 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.06g
-8-
(0.2)
+ 0.05 0.2 0
0.4
(1.75)
0.45 0.15

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